1. Field of the Invention
The present invention relates to a counter and, more particularly, to an up/down convertible counter.
2. Background of the Related Art FIG. 1 illustrates a related up/down counter. A first inverter I1 inverts a mode selection signal MS, which determines the function mode of the counter as up or down counter. A third inverter I3 inverts a clock signal CLK having a prescribed clock cycle to provide a standard for the counter's operation.
A first D flipflop DF1 includes a synchronous clock terminal CK for receiving the clock signal CLK, and an inverted synchronous clock terminal CKB for receiving the output signal of the third inverter I3. An output signal Q1 is generated at a positive logic output Q based on a data input D, and a signal at a negative logic output QB, which is an inverted output signal of the positive logic output Q, is fed back into the data input D.
A first AND gate A1 performs a logic AND operation of the output signal of the positive logic output Q of the first D flipflop DF1 and the mode selection signal MS. A second AND gate A2 performs an AND operation between the output signal of the negative logic output QB of the first D flipflop DF1 and that of the first inverter I1. A first OR gate OR1 performs a logic OR operation with the output signals of the first and second AND gates A1 and A2. A fourth inverter I4 inverts the output signal of the first OR gate OR1. For a 3-bit binary counting, the counter includes a second D flipflop DF2 and a third D flipflop DF3 having the same configuration as the first flipflop DF1 to produce output signals Q2 and Q3. Moreover, a second group of logic gates A3, A4, OR2 and I5 are included between the second and third flipflops DF2 and DF3, which is similarly configured as the first group of logic gates A1, A2, OR1 and I4. The output of a second inverter I2 for inverting a reset signal RST to initialize the counter's operation is connected to the inverted resetting terminals RB of all D flipflops DF1, DF2 and DF3.
The related art up/down counter has various disadvantages related to modularity, integration and functionality. For example, as shown in FIG. 1, there are three flipflops and two groups of logic gates for a 3-bit binary up/down counter. As the number of bits increases, the number of logic gate groups increases proportionately, resulting in undesirable chip size increase.